For 3D integration in 130 nm technologies and beyond, a via middle approach is commonly used. Consequently, the TSV-module is implemented as an independent module between middle-of-line (MOL) and back-end-of-line (BEOL) modules. However, with this process flow an additional oxide deposition step is required for TSV isolation such that there are two deposition steps, a source/drain contact isolation layer deposition and a TSV liner deposition. More specifically, approximately 200 nm of TSV trench isolation oxide at 100% step coverage is deposited on top of an isolation layer to form the TSV liner and then the TSV liner must be completely removed down to the contact layer during the TSV chemical mechanical polishing (CMP) process to form the TSV. This can lead to a decreased pre-metal dielectric (PMD) thickness and increased non-uniformity across the wafer. In addition, the full front-end-of-line (FEOL) and MOL oxide stack has to be opened during the TSV etch process.
A need therefore exists for methodology for forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device.